A long-recognized important objective in the constant advancement of monolithic IC (Integrated Circuit) technology is the scaling-down of IC dimensions. Such scaling-down of IC dimensions reduces area capacitance and is critical to obtaining higher speed performance of integrated circuits. Moreover, reducing the area of an IC die leads to higher yield in IC fabrication. Such advantages are a driving force to constantly scale down IC dimensions.
Referring to FIG. 1, a common component of a monolithic IC is a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) 100 which is fabricated within a semiconductor substrate 102. The scaled down MOSFET 100 having submicron or nanometer dimensions includes a drain extension 104 and a source extension 106 formed within an active device area 126 of the semiconductor substrate 102. The drain extension 104 and the source extension 106 are shallow junctions to minimize short-channel effects in the MOSFET 100 having submicron or nanometer dimensions, as known to one of ordinary skill in the art of integrated circuit fabrication.
The MOSFET 100 further includes a drain contact junction 108 with a drain silicide 110 for providing contact to the drain of the MOSFET 100 and includes a source contact junction 112 with a source silicide 114 for providing contact to the source of the MOSFET 100. The drain contact junction 108 and the source contact junction 112 are fabricated as deeper junctions such that a relatively large size of the drain silicide 110 and the source silicide 114 respectively may be fabricated therein to provide low resistance contact to the drain and the source respectively of the MOSFET 100.
The MOSFET 100 further includes a gate dielectric 116 and a gate structure 118 which may be a polysilicon gate. A gate silicide 120 is formed on the polysilicon gate 118 for providing contact to the polysilicon gate 118. The MOSFET 100 is electrically isolated from other integrated circuit devices within the semiconductor substrate 102 by shallow trench isolation structures 121. The shallow trench isolation structures 121 define the active device area 126, within the semiconductor substrate 102, where a MOSFET is fabricated therein.
The MOSFET 100 also includes a spacer 122 disposed on the sidewalls of the polysilicon gate 118 and the gate oxide 116. When the spacer 122 is comprised of silicon nitride (SiN), then a spacer liner oxide 124 is deposited as a buffer layer between the spacer 122 and the sidewalls of the polysilicon gate 118 and the gate oxide 116.
As dimensions of the MOSFET 100 are scaled further down to tens of nanometers, the drain extension 104 and the source extension 106 are desired to be abrupt and shallow junctions to minimize short-channel effects of the MOSFET 100, as known to one of ordinary skill in the art of integrated circuit fabrication. In addition, for enhancing the speed performance of the MOSFET 100 with scaled down dimensions, a high dopant concentration with high activation in the drain extension 104 and the source extension 106 is desired.
In the prior art, dopant within the drain extension 104 and the source extension 106 are activated using an activation RTA (Rapid Thermal Anneal) process. In addition, the silicides 110, 114, 120 are formed with an additional silicidation RTA (Rapid Thermal Anneal) process. The additional silicidation RTA process further heats up the semiconductor wafer 102, and such additional heating may deactivate the dopant within the drain extension 104 and the source extension 106 that have already been fully activated, as known to one of ordinary skill in the art of integrated circuit fabrication.
Such deactivation of the dopant within the drain extension 104 and the source extension 106 decreases the carrier mobility within the drain extension 104 and the source extension 106 and increases the series resistance at the drain and the source of the MOSFET 100. Such increase in series resistance at the drain and the source of the MOSFET 100 degrades the speed performance of the MOSFET 100.
However, the silicidation RTA (Rapid Thermal Anneal) process is desired for forming the silicides 110, 114, and 120 of the MOSFET 100. Thus, a method is desired for forming highly activated shallow abrupt junctions for the drain extension 110 and the source extension 114 of the MOSFET 100 despite the silicidation RTA (Rapid Thermal Anneal) process.